1. Field of the Invention
The present invention relates, in general, to the field of computer systems and techniques for interconnecting various processing or computing elements. More particularly, the present invention relates to a computer system architecture and memory controller having an arbitration interface enabling external devices to access system memory resources cooperatively.
2. Relevant Background
Conventional computer system architecture for single-processor systems include a microprocessor that communicates with other devices through a “system chipset”. The system chipset implements various input/output and controller functions that enable the microprocessor to communicate with external devices such as memory, mass storage, display devices, network interfaces, printers, and the like. A typical system chipset will implement an interface to the microprocessor often referred to as a “front side bus” or “FSB” that couples to high-speed, low-latency, or bandwidth intensive components such as memory. The chipset implements a secondary interface, often referred to as a “peripheral bus” that operates at a lower speed couples to lower speed devices such as mass storage controllers, printers, network interfaces, and the like.
The system chipset is often produced as multiple specialized components. In a typical configuration, a “north bridge” component implements the microprocessor interface and an interface to the memory subsystem. A “south bridge” component implements the peripheral interface. The north bridge and south bridge components are coupled to bridge the peripheral interface with the microprocessor interface. The interface between the microprocessor and memory is a particularly constrained interface for most applications. In most personal computer architectures, it is assumed that one device will have exclusive access to the FSB (e.g., the single microprocessor being coupled to the FSB). Because of this, all memory transactions must be implemented through a port to the north bridge chip. This increases the system memory access time for the external devices. In the case of hybrid computing systems in which the external device is an adaptive processor, this increase in access time reduces the performance benefits of the hybrid system.
In many cases, a direct memory access (DMA) controller is implemented on the peripheral bus, within the north bridge device, or through a DMA port on the north bridge component to manage memory transactions between the peripheral bus and the memory subsystem. DMA controllers are typically designed to support memory transactions with lower speed peripherals coupled through the south bridge device, as opposed to devices that require significant memory bandwidth such as external processors. In other words, the DMA controller supports peripheral memory activity, and so operates at the slower peripheral interface speeds. While DMA controllers relieve the microprocessor from handling all memory operations, the slower speed interface limits the ability to access the memory subsystem at speeds similar to those available to the microprocessor.
The north bridge of a traditional computer system internally arbitrates between the processor, the graphics port, and peripheral devices and DMA controller for access to the system memory bus. Currently, system chipsets do not provide external access to the arbitration logic. Hence, external devices that desire to access the memory subsystem are constrained to use the arbitration mechanisms implemented by the north bridge component.
SMP (symmetric multiprocessing) refers to systems that execute programs using multiple processors that share a common operating system and memory. In symmetric multiprocessing, the processors share memory and the I/O bus or data path. A single copy of the operating system is in charge of all the processors. Because conventional computing system architectures do not enable multiple devices to access the memory bus, implementing systems in which multiple processors share memory is difficult. As a result, SMP systems based on mass-produced components that are designed for conventional architectures have used lower-speed access granted at peripheral bus speeds, or implemented processing components within the memory subsystem. An example of the later implementation is the multi-adaptive processor (MAP™) described in commonly assigned U.S. Pat. No. 6,247,110 (MAP is a trademark or registered trademark of SRC Computers, Inc.).
In view of the above, it is apparent that a need exists for a computing system that exposes the arbitration mechanisms to enable access to a memory subsystem at high speed. Moreover, there is a particular need for system chipset architectures that utilize an externally provided arbitration signal such that a memory subsystem bus can be accessed by multiple agents such as multiple processors and other components that couple to the memory subsystem bus.